1. Field of the Invention
The present invention generally relates to CMOS circuit design, and in particular, to a method and apparatus for estimating power dissipation in CMOS circuits.
2. Description of Related Art
A large class of CMOS integrated circuits have essentially zero static power dissipation. Nearly all of the energy consumed in the operation of these circuits is dissipated charging and discharging capacitive loads within the circuit and driving external loads connected to the circuit. If the external loads are also CMOS integrated circuits, the power dissipated in charging the capacity of the external loads is also dynamic.
Currently, estimating power dissipation in CMOS integrated circuits can only be done with a simulation of the logic therein. Power dissipation can be accurately simulated by processing an activity file generated with the help of a logic simulator together with a library of cell-based power models. However, the accuracy of the result depends upon the set of patterns used to exercise the logic during the simulation and the accuracy of the power models used with the simulator. Moreover, complete netlists are required or the calculations cannot be performed.
Thus, there is a need in the art for an improved method and apparatus for calculating the dynamic power dissipation in CMOS integrated circuits that provides an approximate result without the requirement for a complete netlist and a set of input stimuli.